1. Field of the Invention
The present invention relates in general to a failure simulation method, and more particularly to a technique for determining whether the test vector is capable of detecting an assumed failure in an integrated circuit.
2. Description of the Background Art
FIGS. 24 to 26 are circuit diagrams illustrating a failure simulation method in the background art. FIGS. 24 to 26 show the same circuit which comprises an OR gate 5 having input ends 5a and 5b connected to signal lines 1 and 4, respectively, and an output end connected to a signal line 3, and a flip flop 7 having an input end D connected to the signal line 3 and an inverted output end QC connected to signal lines 4 and 6 in common and a clock end CLK connected to a signal line 2 through which a clock signal is applied. The circuit processes a signal inputted from the signal line 1 and outputs the processed signal to the signal line 6.
The failure simulation method in the background art will be described taking a case of detecting a failure of the signal line 1 stacked at 1.
At first, the first value of the test vector, "1", is applied to the signal line 1 as shown in FIG. 24. No matter whether the signal line 1 experiences a failure of being stacked at 1 (SA1) or not, the value "1" is applied to the input end 5a of the OR gate 5. Accordingly, the OR gate 5 outputs "1", to the signal line 3, regardless of the logical value on the signal line 4. Then, the value "1" is applied to the input end D of the flip flop 7.
When an activated clock signal (hereinafter, referred to as "P") propagates on the signal line 2, the inverted output end QC outputs the value "0" to propagate on the signal lines 4 and 6. Although the value "0" on the signal line 4 is applied to the input end 5b of the OR gate 5, the OR gate 5 outputs the value "1" and therefore the signal line 3 still propagates the value "1".
Next, the second value of the test vector, "0", is applied to the signal line 1. If the signal line 1 is in a normal condition, the OR gate 5 receives the value "0" from the signal line 4 and then outputs the same value "0" to the signal line 3, as shown in FIG. 25. When "P" is on the signal line 2, the inverted output end QC of the flip flop 7 outputs the value "1" to the signal line 6.
Thus, if the circuit has no failure, the sequence of applications of the first test vector value "1", "P", the second test vector value "0", and again "P" results in the sequence of propagations of "0", "1" on the signal line 6.
On the other hand, if the signal line 1 experiences the failure of SA1, as shown in FIG. 26, the input end 5a of the OR gate 5 receives the value "1" even when the second value of the test vector "0" is applied to the signal line 1. Accordingly, the value "1" propagates on the signal line 3. When "P" is on the signal line 2, the inverted output end QC outputs the value "0".
Thus, if the circuit has such a failure that the signal line 1 is stacked at 1, the sequence of applications of the first test vector value "1", "P", the second test vector value "0", and again "P" results in the sequence of propagations of "0", "0" on the signal line 6.
In other words, the sequence of applications of the test vector values "1", "0" with timing of the propagation of "P" on the signal line 2 and the check of the sequence of output values on the signal line 6 can detect whether the signal line 1 experiences the failure of SA1. The sequence of output values "0", "1" indicates that the circuit is in a normal condition and "0", "0" indicates that the circuit has the failure of the signal line 1 stacked at 1.
Therefore, it is possible to judge that the test vector "1", "0" applied to the signal line 1 is capable of detecting the failure of the signal line 1 stacked at 1 in the circuit shown in FIGS. 24 to 26.
However, the failure simulation system in the background art is not capable of detecting a failure of the signal line 1 stacked at 0 (SA0). FIG. 27 shows the same circuit as FIG. 26 with the signal line 1 stacked at 0.
In this case, no matter whether the test vector value applied to the signal line 1 is "1" or "0", the input end 5a of the OR gate 5 receives the value "0". Then, the value applied to the input end 5b of the OR gate 5 propagates on the signal line 3. The value outputted from the inverted output end QC of the flip flop 7 is undefined, and so is the value on the signal line 4. The simulation proceeds with an undefined value "X" propagating on the signal line 4. The undefined value "X" also propagates on the signal line 3, and therefore the value on the signal line 4 after the propagation of "P" on the signal line 2 is still undefined. In other words, the value on the signal line 4 remains "X" (undefined) all the way of the simulation.
In detecting the failure of the signal line 1 stacked at 1, it is possible to generate the test vector which is capable of detecting the failure since the value from the inverted output end QC of the flip flop 7 is reset to the value "0". On the other hand, in detecting the failure of the signal line 1 stacked at 0, the values on the signal lines 3 and 4 are not defined since the value from the inverted output end QC of the flip flop 7 can not be reset, whatever is applied to the signal line 1 or however often "P" is given to the signal line 2.
In other words, there is a problem that it is extremely difficult to determine the capability of any test vector for detecting the failure of the signal line 1 stacked at 0 in the circuit of FIGS. 24 to 27.